# © Copyright 2021 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

set_property PACKAGE_PIN F2 [get_ports reset_rtl_0]
set_property IOSTANDARD LVCMOS12 [get_ports reset_rtl_0]

set_property IOSTANDARD DIFF_SSTL12 [get_ports diff_clock_rtl_0_clk_n]

set_property PACKAGE_PIN AM6 [get_ports diff_clock_rtl_0_clk_p]
set_property PACKAGE_PIN AN6 [get_ports diff_clock_rtl_0_clk_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports diff_clock_rtl_0_clk_p]

set_property PACKAGE_PIN AJ16 [get_ports {ddr4_rtl_0_dq[0]}]
set_property PACKAGE_PIN AJ17 [get_ports {ddr4_rtl_0_dq[1]}]
set_property PACKAGE_PIN AM15 [get_ports {ddr4_rtl_0_dq[2]}]
set_property PACKAGE_PIN AM14 [get_ports {ddr4_rtl_0_dq[3]}]
set_property PACKAGE_PIN AJ19 [get_ports {ddr4_rtl_0_dq[4]}]
set_property PACKAGE_PIN AK19 [get_ports {ddr4_rtl_0_dq[5]}]
set_property PACKAGE_PIN AL15 [get_ports {ddr4_rtl_0_dq[6]}]
set_property PACKAGE_PIN AL16 [get_ports {ddr4_rtl_0_dq[7]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr4_rtl_0_dqs_t[0]}]
set_property PACKAGE_PIN AL18 [get_ports {ddr4_rtl_0_dqs_c[0]}]

set_property PACKAGE_PIN AV4 [get_ports {ddr4_rtl_0_dq[8]}]
set_property PACKAGE_PIN AU4 [get_ports {ddr4_rtl_0_dq[9]}]
set_property PACKAGE_PIN AV3 [get_ports {ddr4_rtl_0_dq[10]}]
set_property PACKAGE_PIN AW3 [get_ports {ddr4_rtl_0_dq[11]}]
set_property PACKAGE_PIN AR2 [get_ports {ddr4_rtl_0_dq[12]}]
set_property PACKAGE_PIN AT2 [get_ports {ddr4_rtl_0_dq[13]}]
set_property PACKAGE_PIN AU2 [get_ports {ddr4_rtl_0_dq[14]}]
set_property PACKAGE_PIN AV2 [get_ports {ddr4_rtl_0_dq[15]}]
set_property PACKAGE_PIN AR3 [get_ports {ddr4_rtl_0_dqs_t[1]}]
set_property PACKAGE_PIN AT3 [get_ports {ddr4_rtl_0_dqs_c[1]}]

set_property PACKAGE_PIN AU5 [get_ports {ddr4_rtl_0_dq[16]}]
set_property PACKAGE_PIN AT5 [get_ports {ddr4_rtl_0_dq[17]}]
set_property PACKAGE_PIN AT6 [get_ports {ddr4_rtl_0_dq[18]}]
set_property PACKAGE_PIN AU6 [get_ports {ddr4_rtl_0_dq[19]}]
set_property PACKAGE_PIN AR4 [get_ports {ddr4_rtl_0_dq[20]}]
set_property PACKAGE_PIN AR5 [get_ports {ddr4_rtl_0_dq[21]}]
set_property PACKAGE_PIN AV6 [get_ports {ddr4_rtl_0_dq[22]}]
set_property PACKAGE_PIN AW5 [get_ports {ddr4_rtl_0_dq[23]}]
set_property PACKAGE_PIN AR7 [get_ports {ddr4_rtl_0_dqs_t[2]}]
set_property PACKAGE_PIN AT7 [get_ports {ddr4_rtl_0_dqs_c[2]}]

set_property PACKAGE_PIN AR9 [get_ports {ddr4_rtl_0_dq[24]}]
set_property PACKAGE_PIN AR8 [get_ports {ddr4_rtl_0_dq[25]}]
set_property PACKAGE_PIN AV9 [get_ports {ddr4_rtl_0_dq[26]}]
set_property PACKAGE_PIN AW9 [get_ports {ddr4_rtl_0_dq[27]}]
set_property PACKAGE_PIN AT10 [get_ports {ddr4_rtl_0_dq[28]}]
set_property PACKAGE_PIN AU10 [get_ports {ddr4_rtl_0_dq[29]}]
set_property PACKAGE_PIN AV7 [get_ports {ddr4_rtl_0_dq[30]}]
set_property PACKAGE_PIN AV8 [get_ports {ddr4_rtl_0_dq[31]}]
set_property PACKAGE_PIN AW11 [get_ports {ddr4_rtl_0_dqs_t[3]}]
set_property PACKAGE_PIN AW10 [get_ports {ddr4_rtl_0_dqs_c[3]}]

set_property PACKAGE_PIN P37 [get_ports {ddr4_rtl_0_dq[32]}]
set_property PACKAGE_PIN R37 [get_ports {ddr4_rtl_0_dq[33]}]
set_property PACKAGE_PIN T37 [get_ports {ddr4_rtl_0_dq[34]}]
set_property PACKAGE_PIN R38 [get_ports {ddr4_rtl_0_dq[35]}]
set_property PACKAGE_PIN N39 [get_ports {ddr4_rtl_0_dq[36]}]
set_property PACKAGE_PIN N38 [get_ports {ddr4_rtl_0_dq[37]}]
set_property PACKAGE_PIN U39 [get_ports {ddr4_rtl_0_dq[38]}]
set_property PACKAGE_PIN V39 [get_ports {ddr4_rtl_0_dq[39]}]
set_property PACKAGE_PIN U38 [get_ports {ddr4_rtl_0_dqs_t[4]}]
set_property PACKAGE_PIN T38 [get_ports {ddr4_rtl_0_dqs_c[4]}]

set_property PACKAGE_PIN AW16 [get_ports {ddr4_rtl_0_dq[40]}]
set_property PACKAGE_PIN AW17 [get_ports {ddr4_rtl_0_dq[41]}]
set_property PACKAGE_PIN AW19 [get_ports {ddr4_rtl_0_dq[42]}]
set_property PACKAGE_PIN AW20 [get_ports {ddr4_rtl_0_dq[43]}]
set_property PACKAGE_PIN AW14 [get_ports {ddr4_rtl_0_dq[44]}]
set_property PACKAGE_PIN AW15 [get_ports {ddr4_rtl_0_dq[45]}]
set_property PACKAGE_PIN AU16 [get_ports {ddr4_rtl_0_dq[46]}]
set_property PACKAGE_PIN AV16 [get_ports {ddr4_rtl_0_dq[47]}]
set_property PACKAGE_PIN AV19 [get_ports {ddr4_rtl_0_dqs_t[5]}]
set_property PACKAGE_PIN AV18 [get_ports {ddr4_rtl_0_dqs_c[5]}]

set_property PACKAGE_PIN AU18 [get_ports {ddr4_rtl_0_dq[48]}]
set_property PACKAGE_PIN AU19 [get_ports {ddr4_rtl_0_dq[49]}]
set_property PACKAGE_PIN AU20 [get_ports {ddr4_rtl_0_dq[50]}]
set_property PACKAGE_PIN AT20 [get_ports {ddr4_rtl_0_dq[51]}]
set_property PACKAGE_PIN AT15 [get_ports {ddr4_rtl_0_dq[52]}]
set_property PACKAGE_PIN AU15 [get_ports {ddr4_rtl_0_dq[53]}]
set_property PACKAGE_PIN AR18 [get_ports {ddr4_rtl_0_dq[54]}]
set_property PACKAGE_PIN AR17 [get_ports {ddr4_rtl_0_dq[55]}]
set_property PACKAGE_PIN AR19 [get_ports {ddr4_rtl_0_dqs_t[6]}]
set_property PACKAGE_PIN AT18 [get_ports {ddr4_rtl_0_dqs_c[6]}]

set_property PACKAGE_PIN AP15 [get_ports {ddr4_rtl_0_dq[56]}]
set_property PACKAGE_PIN AR15 [get_ports {ddr4_rtl_0_dq[57]}]
set_property PACKAGE_PIN AP17 [get_ports {ddr4_rtl_0_dq[58]}]
set_property PACKAGE_PIN AP16 [get_ports {ddr4_rtl_0_dq[59]}]
set_property PACKAGE_PIN AN14 [get_ports {ddr4_rtl_0_dq[60]}]
set_property PACKAGE_PIN AP14 [get_ports {ddr4_rtl_0_dq[61]}]
set_property PACKAGE_PIN AM18 [get_ports {ddr4_rtl_0_dq[62]}]
set_property PACKAGE_PIN AM19 [get_ports {ddr4_rtl_0_dq[63]}]
set_property PACKAGE_PIN AN19 [get_ports {ddr4_rtl_0_dqs_t[7]}]
set_property PACKAGE_PIN AN18 [get_ports {ddr4_rtl_0_dqs_c[7]}]

set_property PACKAGE_PIN AU11 [get_ports {ddr4_rtl_0_dq[64]}]
set_property PACKAGE_PIN AV11 [get_ports {ddr4_rtl_0_dq[65]}]
set_property PACKAGE_PIN AR12 [get_ports {ddr4_rtl_0_dq[66]}]
set_property PACKAGE_PIN AR13 [get_ports {ddr4_rtl_0_dq[67]}]
set_property PACKAGE_PIN AR10 [get_ports {ddr4_rtl_0_dq[68]}]
set_property PACKAGE_PIN AP11 [get_ports {ddr4_rtl_0_dq[69]}]
set_property PACKAGE_PIN AV13 [get_ports {ddr4_rtl_0_dq[70]}]
set_property PACKAGE_PIN AU13 [get_ports {ddr4_rtl_0_dq[71]}]
set_property PACKAGE_PIN AV12 [get_ports {ddr4_rtl_0_dqs_t[8]}]
set_property PACKAGE_PIN AW12 [get_ports {ddr4_rtl_0_dqs_c[8]}]

set_property PACKAGE_PIN AK9 [get_ports {ddr4_rtl_0_adr[0]}]
set_property PACKAGE_PIN AK8 [get_ports {ddr4_rtl_0_adr[1]}]
set_property PACKAGE_PIN AP10 [get_ports {ddr4_rtl_0_adr[2]}]
set_property PACKAGE_PIN AM9 [get_ports {ddr4_rtl_0_adr[3]}]
set_property PACKAGE_PIN AP9 [get_ports {ddr4_rtl_0_adr[4]}]
set_property PACKAGE_PIN AM8 [get_ports {ddr4_rtl_0_adr[5]}]
set_property PACKAGE_PIN AN9 [get_ports {ddr4_rtl_0_adr[6]}]
set_property PACKAGE_PIN AN7 [get_ports {ddr4_rtl_0_adr[7]}]
set_property PACKAGE_PIN AN8 [get_ports {ddr4_rtl_0_adr[8]}]

set_property PACKAGE_PIN AK6 [get_ports {ddr4_rtl_0_adr[9]}]
set_property PACKAGE_PIN AL8 [get_ports {ddr4_rtl_0_adr[10]}]
set_property PACKAGE_PIN AL7 [get_ports {ddr4_rtl_0_adr[11]}]
set_property PACKAGE_PIN AK7 [get_ports {ddr4_rtl_0_adr[12]}]
set_property PACKAGE_PIN AM4 [get_ports {ddr4_rtl_0_adr[13]}]
set_property PACKAGE_PIN AP4 [get_ports {ddr4_rtl_0_adr[14]}]
set_property PACKAGE_PIN AM5 [get_ports {ddr4_rtl_0_adr[15]}]
set_property PACKAGE_PIN AL6 [get_ports {ddr4_rtl_0_adr[16]}]

set_property PACKAGE_PIN AK17 [get_ports {ddr4_rtl_0_dm_n[0]}]
set_property PACKAGE_PIN AT1 [get_ports {ddr4_rtl_0_dm_n[1]}]
set_property PACKAGE_PIN AW7 [get_ports {ddr4_rtl_0_dm_n[2]}]
set_property PACKAGE_PIN AT8 [get_ports {ddr4_rtl_0_dm_n[3]}]
set_property PACKAGE_PIN R39 [get_ports {ddr4_rtl_0_dm_n[4]}]
set_property PACKAGE_PIN AU14 [get_ports {ddr4_rtl_0_dm_n[5]}]
set_property PACKAGE_PIN AT17 [get_ports {ddr4_rtl_0_dm_n[6]}]
set_property PACKAGE_PIN AN17 [get_ports {ddr4_rtl_0_dm_n[7]}]
set_property PACKAGE_PIN AT13 [get_ports {ddr4_rtl_0_dm_n[8]}]

set_property PACKAGE_PIN AJ11 [get_ports {ddr4_rtl_0_ck_t[0]}]
set_property PACKAGE_PIN AJ10 [get_ports {ddr4_rtl_0_ck_c[0]}]
set_property PACKAGE_PIN AM13 [get_ports {ddr4_rtl_0_odt[0]}]
set_property PACKAGE_PIN AL12 [get_ports {ddr4_rtl_0_cs_n[0]}]
set_property PACKAGE_PIN AN11 [get_ports {ddr4_rtl_0_cke[0]}]

set_property PACKAGE_PIN AL5 [get_ports {ddr4_rtl_0_bg[0]}]
set_property PACKAGE_PIN AK5 [get_ports {ddr4_rtl_0_bg[1]}]
set_property PACKAGE_PIN AP7 [get_ports {ddr4_rtl_0_ba[0]}]
set_property PACKAGE_PIN AK3 [get_ports {ddr4_rtl_0_ba[1]}]
set_property PACKAGE_PIN AW4 [get_ports ddr4_rtl_0_reset_n]
set_property PACKAGE_PIN AP6 [get_ports ddr4_rtl_0_act_n]


create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/ddr4_0/inst/u_ddr4_infrastructure/dbg_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awqos[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awqos[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awqos[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awqos[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awprot[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awprot[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awprot[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awlock[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 64 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[0]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[1]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[2]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[3]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[4]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[5]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[6]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[7]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[8]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[9]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[10]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[11]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[12]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[13]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[14]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[15]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[16]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[17]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[18]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[19]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[20]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[21]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[22]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[23]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[24]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[25]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[26]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[27]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[28]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[29]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[30]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[31]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[32]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[33]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[34]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[35]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[36]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[37]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[38]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[39]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[40]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[41]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[42]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[43]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[44]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[45]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[46]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[47]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[48]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[49]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[50]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[51]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[52]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[53]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[54]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[55]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[56]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[57]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[58]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[59]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[60]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[61]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[62]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_mask[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awlen[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 3 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awid[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awid[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awid[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 2 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awburst[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awburst[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 33 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[31]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awaddr[32]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 3 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arsize[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arsize[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arsize[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 4 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arqos[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arqos[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arqos[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arqos[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 3 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arprot[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arprot[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arprot[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arlock[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arlen[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 4 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arcache[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arcache[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arcache[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arcache[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 2 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_arburst[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_arburst[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 33 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[31]} {design_1_i/ddr4_0/c0_ddr4_s_axi_araddr[32]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 27 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[3]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[4]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[5]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[6]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[7]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[8]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[9]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[10]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[11]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[12]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[13]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[14]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[15]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[16]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[17]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[18]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[19]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[20]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[21]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[22]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[23]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[24]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[25]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[26]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[27]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[28]} {design_1_i/ddr4_0/inst/c0_ddr4_app_addr[29]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 512 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[0]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[1]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[2]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[3]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[4]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[5]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[6]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[7]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[8]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[9]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[10]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[11]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[12]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[13]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[14]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[15]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[16]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[17]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[18]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[19]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[20]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[21]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[22]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[23]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[24]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[25]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[26]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[27]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[28]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[29]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[30]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[31]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[32]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[33]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[34]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[35]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[36]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[37]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[38]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[39]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[40]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[41]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[42]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[43]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[44]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[45]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[46]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[47]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[48]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[49]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[50]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[51]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[52]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[53]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[54]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[55]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[56]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[57]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[58]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[59]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[60]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[61]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[62]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[63]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[64]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[65]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[66]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[67]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[68]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[69]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[70]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[71]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[72]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[73]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[74]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[75]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[76]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[77]} {design_1_i/ddr4_0/inst/c0_ddr4_app_wdf_data[78]} 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create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 2 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {design_1_i/ddr4_0/inst/c0_ddr4_app_cmd[0]} {design_1_i/ddr4_0/inst/c0_ddr4_app_cmd[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[0]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[1]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[2]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[3]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[4]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[5]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[6]} {design_1_i/ddr4_0/inst/c0_ddr4_app_ecc_multiple_err[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 512 [get_debug_ports u_ila_0/probe20]
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{design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[479]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[480]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[481]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[482]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[483]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[484]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[485]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[486]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[487]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[488]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[489]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[490]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[491]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[492]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[493]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[494]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[495]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[496]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[497]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[498]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[499]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[500]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[501]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[502]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[503]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[504]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[505]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[506]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[507]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[508]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[509]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[510]} {design_1_i/ddr4_0/inst/c0_ddr4_app_rd_data[511]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 3 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_awsize[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awsize[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_awsize[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 3 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_bid[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_bid[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_bid[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 2 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_bresp[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_bresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 32 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_araddr[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 32 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awaddr[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property port_width 2 [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_bresp[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_bresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property port_width 2 [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rresp[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property port_width 32 [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[20]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[21]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[22]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[23]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[24]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[25]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[26]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[27]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[28]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[29]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[30]} {design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property port_width 128 [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rdata[20]} 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create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property port_width 3 [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_rid[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rid[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rid[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property port_width 2 [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_rresp[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_rresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property port_width 128 [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[15]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[16]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[17]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[18]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[19]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[20]} 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{design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[109]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[110]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[111]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[112]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[113]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[114]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[115]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[116]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[117]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[118]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[119]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[120]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[121]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[122]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[123]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[124]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[125]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[126]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wdata[127]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property port_width 16 [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[0]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[1]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[2]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[3]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[4]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[5]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[6]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[7]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[8]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[9]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[10]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[11]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[12]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[13]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[14]} {design_1_i/ddr4_0/c0_ddr4_s_axi_wstrb[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_arready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_arvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_awready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_awvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_bready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_bvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_arready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
connect_debug_port u_ila_0/probe42 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_arvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
connect_debug_port u_ila_0/probe43 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
connect_debug_port u_ila_0/probe44 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_awvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
connect_debug_port u_ila_0/probe45 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_bready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
connect_debug_port u_ila_0/probe46 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_bvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
connect_debug_port u_ila_0/probe47 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
connect_debug_port u_ila_0/probe48 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
connect_debug_port u_ila_0/probe49 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
connect_debug_port u_ila_0/probe50 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_ctrl_wvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
connect_debug_port u_ila_0/probe51 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_rlast]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
connect_debug_port u_ila_0/probe52 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_rready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
connect_debug_port u_ila_0/probe53 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
connect_debug_port u_ila_0/probe54 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_wlast]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
connect_debug_port u_ila_0/probe55 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_wready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
connect_debug_port u_ila_0/probe56 [get_nets [list design_1_i/ddr4_0/c0_ddr4_s_axi_wvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
connect_debug_port u_ila_0/probe57 [get_nets [list design_1_i/ddr4_0/c0_init_calib_complete]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
